1. Field of the Invention
This invention relates to communications links between integrated circuits and, more particularly, to testing of communications links between integrated circuits during system operation.
2. Description of the Related Art
Increasing bandwidth demands on communications links between integrated circuits have led to designs that replace wide parallel links with very high-speed serial links, thereby potentially simplifying circuit board layout and reducing timing skew problems while achieving higher net bandwidth. Multi-gigabit-per-second serial links have become a common means for communicating data between integrated circuits on a single board or across a backplane between boards. In a typical serial communications link, a Serializer/Deserializer (SerDes) is used to convert a set of parallel signals to a serial bit stream and vice versa. Often, a multiple-byte set of signals is divided into 8-bit segments, each segment is converted into a serial bit stream, and the serial bit streams are grouped together to form a communications link. In such an arrangement, each serial bit stream may be referred to as a lane and a link comprises several lanes.
At multi-gigabit per second speeds, the analog properties of digital waveforms affect the performance of a serial communications link. In particular, the voltage levels representing “0” and “1” and the timing of bit transitions compared to a reference clock may vary from bit to bit within a digital waveform. These voltage and timing variations are caused, in part, by noise radiated from nearby electrical signals and by electrical noise on power and ground connections. Voltage and timing of a particular bit are also affected by the values of other bits that are being transmitted and the history of bits transmitted over a given lane and its neighboring lanes.
A well-known test for characterizing a serial communications lane is the eye scan. In an eye scan, a pattern of ones and zeros is transmitted over a lane and the received signal is sampled either at a rate that is many times the bit rate or at many different phases within a bit time. The received signal is also independently sampled over a range of input voltage levels. The resulting samples are assembled to form a digital waveform. Time-slices of the digital waveform are superimposed to form a pattern that resembles an open eye. The size of the opening is a measure of the voltage and timing margin available on the lane. Eye scan testing is typically used for characterization and verification of individual components prior to their installation into a system assembly.
Once components are assembled into a system, the system operating environment presents stresses that may significantly alter the results of an eye scan. For instance, variability in the system assembly, electrical noise from nearby circuitry, and electrical noise from power and ground connections may affect the time and voltage margins seen in an eye scan, and consequently the performance of a serial communications lane. Unfortunately, the variability of the factors listed above may result in an assembly containing a communications link with poor time and/or voltage margins despite the fact that all components have passed individual screening tests. Testing with the actual electrical stress environment (including an applied stress stimulus on the lane under test as well as on nearby circuitry) and representative samples of system assemblies that account for variability in the quality of soldering, connector mating, handling, and general workmanship can be expected to more readily expose defects and poor margin performance than conventional component-level testing methods. Also, the characteristics of a given system assembly that may lead to an early decay of performance in the field may not be detected by conventional quality screening performed in a test environment. Therefore, a way to test individual communications lanes under normal system operating conditions is desired.